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RDRAM Moves Along Rambus spec nears finish line but hurdles await By Anthony Cataldo, EE Times San Mateo, Calif. --The specification for the next-generation Direct Rambus DRAM (RDRAM) is nearly finished by Rambus Inc. and Intel Corp., though memory makers say much process-engineering work remains before the devices will be ready for mass production. Chief among the problems is power consumption, sources said. "To keep power consumption down, we have to go to 2.5 V, and to hit the 800-MHz target at 2.5 V is a challenge," said Hidemori Inukai, in charge of memory-product development at NEC Corp. (Tokyo), one of 11 Rambus licensees. To get there will require an aggressive, 0.22-micron process, he said. Reaching adequate yields for the new devices is also an issue. "There is no question that 800 MHz is achievable, but at what yields?" said Inukai. "Currently we are making Rambus DRAMs that operate at 600 MHz, but the yields are 30 to 40 percent, and that is not good." Rambus countered that a yield of 30 percent to 40 percent is good at such an early stage in the production learning curve. Rambus said it is about a month away from finishing a new protocol that promises to boost memory bandwidth to 1.6 Gbytes/second, and it expects to officially announce the specification in October. Various pieces of test silicon will be produced before the end of the year, said Subodh Toprani, vice president of marketing for the Mountain View, Calif., company, "In terms of implementing it in silicon, it's much further along than people realize," Toprani said. "We've transferred huge chunks of circuit technology to the partners. Most of the definition work is all completed. Some silicon should be coming out very shortly." Last week, Rambus added two new vendors--Texas Instruments Inc. and Fujitsu Ltd.--to its roster of partners. That makes 11 DRAM licensees that have pledged to develop Direct RDRAMs, memories running at 800 MHz with a peak bandwidth of 1.6 Gbytes/s. Unlike today's synchronous or Rambus-based DRAMs, sustained bandwidth will be less than 10 percent below peak. The protocol is designed to be tightly coupled with the DRAM controller in the core logic, which Intel is expected to introduce in late 1998 or 1999. "We're providing as much direct access to the core of the DRAM controller as is practical," Toprani said. Besides improving the protocol, Rambus has doubled the size of the interface channel to 16 bits, and added a delay-locked loop and current-compensation circuits to the interface to make it more robust when running at high frequencies. Even so, Toprani characterized the changes as minor. "We do not have to invent anything new," he said. NEC said that engineering samples of the 72-Mbit Direct RDRAM are expected to be ready by the third quarter of 1998, with mass production "hopefully" starting in the fourth quarter. The first design, with a by-9 configuration for the parity checking used in high-end systems, will be followed by "the real commercial part," Inukai said: a 64-Mbit design with a by-8 configuration, for desktops. Power consumption is a major concern, Inukai said. "The power consumption of the I/Os could be huge, and the real bottleneck for these high-frequency memories is power. In that sense, the SLDRAM [formerly called Synclink] may be better." Hitting the 2.5-V target is going to take some leading-edge process technology. Most companies will probably have to port Direct RDRAMs to their 0.25-micron, 256-Mbit DRAM process, said Ramesh Gidwani, vice president of MOS memory marketing for Texas Instruments (Dallas), which plans to implement the forthcoming Direct Rambus and existing Concurrent Rambus interface on DRAMs, digital signal processors and networking devices. "The 64-Mbit DRAM is 3.3 V, so you have to make a technology node jump," he said. "I would say it's closer to 0.2-micron technology. We will use our development effort on that class of technology at the 64-meg level." Like Inukai, he said the first Direct RDRAM devices won't be ready until at least the latter half of 1998. (Next article.)
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