In mid-2015, Intel (INTC -1.79%) CEO Brian Krzanich told investors that the company intended to put off the high-volume manufacturing of the lead product manufactured on its upcoming 10-nanometer technology, known as Cannon Lake, by about a year.

The plan was to introduce a third wave of products made using its 14-nanometer technology in the second half of 2016; then, at some point in the second half of 2017, it would launch Cannon Lake.

A die shot of Intel's 22-nanometer Haswell-EP server processor, which has 18 cores embedded on a single piece of silicon.

A die shot of Intel's Haswell-EP server chip. Image source: Intel.

That's still the plan, as of the company's most recent investor meeting.

However, in the 2015 earnings call, Krzanich said something else. In trying to put down the company's contract chip manufacturing competitors, he said that the company would use Cannon Lake to produce a "large percentage of [Intel's] CPUs in volume in the second half of 2017."

"When we say second half of 2017, we're talking about millions of units and large volumes," he said.

Fast-forward to the commentary at Intel's 2017 investor meeting: The company is now committing to shipping these Cannon Lake chips in the second half of 2017 with "volume in the first half of [2018]."

That, my dear readers, is another delay.

To rub further salt in the wound, the company also finally admitted that some (and the reality, based on various credible leaks, is that it's likely to be most) of the 8th-generation Core processors for personal computers that will begin rolling out in the second half of 2017 will be manufactured on a further-enhanced variant of the company's 14-nanometer technology.

In other words, not only is Intel delaying its 10-nanometer roll out, but it's also starting to look as though the chipmaker won't convert a "large" portion of its CPU volumes to 10-nanometer until the second half of 2018 at the earliest.

Impact on the business

To be blunt, I don't think this delay will negatively impact Intel's business or the stock price. The company has made it clear that it will release new and improved products beginning in the second half of 2017 to meet its customers' demands. Whether those chips are manufactured on 10-nanomter or a performance-enhanced flavor of its 14-nanometer technology probably isn't that important to either system vendors or end customers.

Indeed, given a choice between producing chips on an immature 10-nanometer technology with potential yield issues and high initial wafer costs, and producing chips with relatively low wafer costs on an extremely mature 14-nanometer technology that has had many generations of performance enhancements applied to it, it's clear which one would maximize Intel's bottom line. 

If anything, moving too much of its volume to 10-nanometer before the technology is high yielding and cost effective could destroy shareholder value. 

Intel still needs to pull it together

The chipmaker cannot stay on its 14-nanometer technology forever -- after 8th generation Core, the company will need to make the leap to 10-nanometer technology (possibly a performance enhanced 10-nanometer+ variant) to build its 9th generation Core processors.

This means that Intel has a little over a year to work out the kinks on its 10-nanometer technology to make it economically viable for mass production.

I suspect that the low-power Cannon Lake chip will represent little more than an opportunity for Intel to iron out the kinks with its 10-nanometer process while extracting some revenue from what are essentially "salable test chips." 

And, to be blunt again, the bar for "economically viable" is quite high. From a cost structure perspective, Intel will be transitioning from a manufacturing technology that has been in production for more than four years at that point to a technology that will have barely been in production for a year.

Intel has publicly stated that it intends to expand the operating profit margin of its Client Computing Group over the next three years. If it's to achieve that, the company can't absorb a generation-over-generation cost structure increase, which means 10-nanometer must be in top shape come late 2018.