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August 14, 2000

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Subject:  Moore's Law and its Effect on Memory Design
Author:  mschmit

I've taught computer architecture courses off and on for ~7 years. Hopefully, for those not familiar with Moore's Law and its affect on CPU and memory design, the following few paragraphs will help. (Note that this is a brief summary of a complex subject)

Moore's Law states that the number of transistors on a chip will double about every 18-24 months. This isn't a true law, just an observation/prediction made by Gordon Moore in 1965 prior to co-founding Intel. At some point the laws of physics will stop Moore's Law and computer designers will have to turn to other technologies to increase performance. But this is at least 10 years away, maybe 15 or 20. (Also note that it says nothing about performance. People often misquote Moore, stating that CPU power doubles every ~2 yrs. While this also, approximately, happens that is like saying it gets light during the day so that you can see the sun.)

The real reason for this progression is that the equipment used to make chips improves such that the line size (width of a trace) decreases about 15% every year. (15% smaller for two years is: 0.85 x 0.85 = 0.72 in linear length; in square area: 0.72 x 0.72 = 0.52 or about half the area). So given a fixed design, in ~2 years a couple of things happen. First, the product gets cheaper (we'll ignore this, but it makes investing fun) and second the smaller size means less power consumption. Less power means less heat, less heat means the MHz can be increased without the part failing.

Given several shrinks of the same CPU micro-architecture, the chips will get faster and faster. The same thing would happen for a given memory chip design (bit count), smaller means faster.

As time goes on, we can also use the fact that transistors are smaller to use more transistors keeping the die size about the same. For memory chips this doesn't make them faster, it just makes a single chip hold more data. For CPUs, the new transistors are used to make the CPU more powerful, i.e. handle more bits per calculation and/or handle more instructions per cycle. (i.e. going from the 386 to 486 to Pentium, etc.)

A careful observer will now note an interesting dilemma. That is, all things being equal, if both a CPU and a memory chip go through many generations, the CPU will get two types of performance boosts, the memory chip only one. The CPU gets one type of improvement from smart use of the new transistors (wider operations, more instructions per cycle, etc.) and one from the clock speed increase. Memory chips get a performance boost only from the clock speed increase.

Thus, this is the cause for an ever increasing gap between the performance of CPUs and the performance of memory. There is no be-all end-all solution to this. Caches overcome most of the difference, but even a 90% cache hit rate means severe and ever-increasing penalty for the 10% of misses...i.e. back to where we started. In addition, every so often there are some minor improvements in the way memory addresses are sent to the memory chips and the data is sent and received. These improvements are generally minor compared to the pace of improvements in CPU performance. (DRAM examples: FP DRAM to EDO DRAM to SDRAM)

<my opinions> This memory performance gap is the reason that so much attention is on Rambus and memory, in general. The Rambus founders understood all this and looked at how the pace of minor improvements in communicating with memory chips could be sped up and/or be more significant. While I don't think that Rambus (the memory) is that dramatic of an improvement (maybe as valuable as 2 or 3 minor changes), it is important. And every improvement is needed. Every improvement also has a ratchet effect � once it is used we never go back and everyone expects that new level of performance. Thus in a few short years, based on Rambus' IP, it will be very difficult (or impossible) to use some type of memory that doesn't infringe on Rambus' patents for any medium to high performance system. </my opinions>


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