Intel Corporation
The Problem with Prescott

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By alan81
February 4, 2004

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I am pretty surprised by the performance and power of the Prescott processor. It is clearly "not ready" yet, compared to my expectations. I think it is at a point where the performance is about the same as 130nm, the power is higher than 130nm, and I bet the cost is about the same as 130nm. So why did Intel introduce the thing? I think there are a few answers to this...

(1) They promised they would, and they need to keep their promises.
This is a pretty weak reason, which is why I think the next one is more important.

(2) 90nm is mostly new capacity in new 300mm factories.
They needed to free up 130nm for several reasons, the most important of which is the new large die, larger cache Xeon's, which need more fab space. As Itanium ramps it will need more fab space too. They need to move to the new socket T, and Grantsdale chipset, which I believe is built on 130nm. Finally, they need to take a factory off-line in order to get it converted to 300mm in time for the 65nm ramp. The trick was making sure that even though 90nm was late and under performing, it did not result in everything behind it also being delayed. The Prescott was "good enough" to set everything in motion.

So what does the future bring with Prescott? Given that it appears they really did go with a 31-stage pipeline (which shocked the heck out of me), yet IPC is about on par is a pretty good engineering feat. With the longer pipeline, and the new process technology, the design should scale to about 3.4Ghz *1.5 (for the pipeline) *1.5 (for the process) which is about 7.5Ghz! I imagine the traditional curves are starting to break down, so perhaps they will not achieve this scaling... but perhaps they will. If this seems really, unreasonable, compare it to the 180nm P3 to the 130nm P4, which includes both a process shift and a significant pipeline extension. The clock rate went from 1Ghz on the P3 to 3.4Ghz on the P4... or a factor of 3.4X faster.

Intel is currently saying that the Prescott will hit 4.0Ghz by the end of the year. This would mean the performance would be about 10% better one year after conversion to a new process technology. The new die is nearly the size of the old (113mm vs. 135, but with an extra layer of metal). Personally, if this is all the performance they can get out of Prescott, I'll give them a "D" on it. If they can get to 5Ghz I will up that to a "C", and 6Ghz will only get them a "B". They will need something north of 6Ghz to get an "A" from me. Of course if they somehow pull a rabbit out of the hat and demonstrate a higher IPC through some magic methods, then the clock rate grading scale would need to be adjusted.

Even though, from an engineering point of view, I am disappointed in what Intel has delivered so far, I am not too concerned from a financial point of view. Product cost is currently very reasonable, and dropping a little bit. The market is doing well and ASP's are holding to slightly rising. AMD has saddled themselves with a large die product that they can not make in significant volume. Even though AMD is getting good mind share in the server market, most of what they are capturing are the cheap seats of 1P or 2P servers. The CPU's in these systems sell for about the same price as desktops, so really is not that much to be concerned about, for now.

Intel has many R&D programs in the pipeline that should solve the Prescott problems. From what I have seen, I bet the most significant issue is gate oxide leakage. I was surprised to see that some of the Prescott chips are operating at 1.5V. The IBM G5 on 90nm operates at 1.0V. The operating voltage directly relates to device power. To operate with the higher voltage, the gate oxide must be fairly thick, or else there would be reliability issues. If the oxide is thicker, then there will be other power and performance issues with the transistors. All of this indicates to me that there are some issues with the silicon process itself, and those issues are in areas that Intel has been investing heavily for the past several years. I am not sure if they will ever truly fix them on the 90nm process. Note that the high K gate dielectric is over 100 times better than the traditional materials. If they can really improve this by 100X, it gives them a whole new region of operation for both much higher performance and much lower power. I doubt they will ever retrofit the 90nm process with this new material, but rather implement it on 65nm. I hope they get this problem solved sooner rather than later.

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