The recent announcement really concerned Itanium, and had little to do with Xeon, although much has been rumored about Xeon. Become a Complete Fool
If we look at Itanium, it started out as a contingency plan in case X86 failed to scale and RISC took over. As it became obvious X86 had legs, Itanium took a second mission to allow Intel to penetrate the lucrative high-end server market and stop alternative architectures like SPARC and POWER. SPARC is all but dead, but POWER lives on. However, POWER is becoming less and less relevant as Apple has now agreed to move to INTC. In addition, the X86 server market continues to expand upward eating into the historically highly profitable territory of proprietary servers.
In this light, Intel's reaction is predictable with decreased focus on Itanium, and increased focus on Xeon. I suspect Intel has contractual commitments to HP regarding Itanium, or it would have been gone a while ago. As it is, they are dedicating a certain amount of resources to it and letting things happen as they may. With the recent slip in Montecito, which I place closer to a year rather than the six months that has been reported, all the other Itanium projects have also slipped a year. This pushes the "common" Reidland Itanium/Xeon platform out a year to 2008. This left the quad core Whitefield Xeon MP, which was the first Merom based Xeon MP product, out in 2008. The Intel commitment to Xeon MP is obvious, as they had a product all planned and ready to go to fill in the 2007 hole left by the slip of the common platform. Itanium has been allowed to slip, but Xeon has not. I think that speaks volumes.
An interesting concern is the competitiveness of the new 2007 Xeon MP platform. I think little is known about it, but actually little is known about how Opteron will perform in this time frame either. Intel is clearly setting themselves up for a fairly expensive platform with a four FSB chipset. However, keep in mind these systems will have 16 cores in them (quad core, four sockets). I suspect the Opteron will be having trouble with all the memory and cache coherency traffic over the HT links. Intel will be having trouble getting enough data up a single FSB to feed all four cores. If AMD is able to go with four FBDIMM channels per socket, I suspect they will have the higher performing solution... but a minimal memory footprint would become 16 memory DIMMS, which is a pretty pricey solution as well.
I think too little is known, and 2007 is too far away to worry too much about what this will mean for the 4-socket space in that time. With the performance gains we are seeing in the 2 socket systems, coupled with the continued move to clusters, I suspect the 4-socket market may be sufficiently small in 2007 that the point becomes moot. We will see.
Just some rambling thoughts on the issues,
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The recent announcement really concerned Itanium, and had little to do with Xeon, although much has been rumored about Xeon.
Become a Complete Fool