In early 2013, SemiAccurate's Charlie Demerjian wrote an interesting piece titled "Why is Intel so secretive about [Xeon] Phi's die?" In the article, Demerjian said sources had told him that the die size of Intel's (INTC 1.53%) 22-nanometer Knights Corner Xeon Phi chip (a specialized co-processor for high-performance computing workloads) was "closer to 700mm^2 than 600."

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If Intel wants to improve margins on these chips -- particularly as their sales grow and become a more impactful part of the company's data center group revenue stream -- it will need to either improve the designs in order to fetch a premium or lower production costs.

While Intel's next-generation 14-nanometer Knights Landing part looks to offer compelling features and specifications, only time will tell if it will be competitive enough to allow the company to raise prices while growing sales volumes. With that in mind, I think it's worth looking at the potential cost structure of the upcoming Knights Landing chip.

Digging deeper into cost structure
Let's assume that, per SemiAccurate's comments, the die size of Knights Corner (the 22-nanometer part) sits at 675 square millimeters. This is a high-performance part built on Intel's high-performance 22-nanometer process, so I'm also going to make the reasonable assumption that the transistor density of the Knights Corner Xeon Phi is roughly equivalent to the reported density of the 662-square-millimeter Haswell-EP.

This would suggest Knights Corner features roughly 5.8 billion transistors. At Intel's November investor meeting, though, data center group chief Diane Bryant claimed the 14-nanometer Knights Corner Xeon Phi chip features 7.1 billion transistors.

If we assume moving to 14-nanometer roughly doubles transistor density, then Knights Landing's die size should stand at about 413 square millimeters. Now, according to Intel, the capital intensity per wafer in moving from 22-nanometer to 14-nanometer goes up by 30%. Notice, though, that the transistor count looks to be up by 22% based on these estimates.

So if it costs X for a wafer of Knights Corner chips, then it will cost 1.3X for a wafer of Knights Landing chips. Assuming similar yields per wafer, if Intel is getting Y good Knights Corner dies, then the smaller die of the Knights Landing chip will allow for approximately 1.76Y good die per wafer (note: for this calculation I employed Silicon Edge's dies per wafer estimator and used the square root of the estimated die sizes for the dimensions).

If the cost per die for a Knights Corner is X/Y and the cost per die of a Knights Landing is (1.3/1.76)(X/Y), then, if I've done my math right, the Knights Landing -- with a better architecture and packed with more transistors -- should actually be about 74% the cost to build as the Knights Corner. Again, this assumes similar yields.

What does this mean?
While the Knights Landing might be cheaper to build from a die perspective, the Knights Landing solutions will, according to AnandTech, be paired with specially designed on-package memory from Micron. This advanced memory might be more expensive than the GDDR5 found on today's Knights Corner boards.

In a nutshell, while I believe that -- if Intel gets 14-nanometer yields sorted out -- the Knights Landing die should be cheaper to build, Intel's gross margin structure on the parts will also be a function of the chip's sales price. This, in my view, will be a function of the performance and power competitiveness of the parts, something that won't be known until the products have launched (Intel claims first systems using Knights Landing in the second half of 2015) and have had some time in the marketplace.