Intel (INTC -9.73%) has been talking about its next-generation processor aimed at high-performance computing applications, known as Knights Landing, for quite some time. At the Hot Chips 2015 conference, Avinash Sodani, chief architect on the Knights Landing project, detailed key aspects of this monster chip.
Let's take a look at what Intel disclosed and what it might mean for the company's high-performance computing chip business.
Knights Landing at a glance
Intel says that the Knights Landing chip features 36 "tiles." Each tile contains two (highly modified) Silvermont processor cores, two 512-bit vector units, and 1 megabyte of L2 cache.
As far as memory goes, all of the Knights Landing variants feature 16 gigabytes of very fast on-package memory. The socketed versions that can be used as stand-alone processors rather than just as co-processors also include six channels of DDR4-2400 memory.
The Knights Landing chips also come with 36 PCIe Gen. 3 lanes and optional on-package Omni-Path interconnect fabric.
All of this means that Knights Landing can deliver more than three teraflops of double-precision computing performance and six teraflops of single-precision performance. Intel also says that scalar performance increases by a factor of three over the prior-generation Knights Corner part.
An all-new processor core
Since Intel is aiming to sell Knights Landing in stand-alone form (i.e., not as an accelerator that requires a host processor), the company has focused on significantly improving the performance of the CPU cores found in each tile.
The CPU is based on the company's Silvermont Atom processor, but with "many changes for [high performance computing]" according to the company's Hot Chips presentation. In short, think of it as a Silvermont core on steroids implemented in a more advanced 14-nanometer process.
On-package Omni-Path interconnect
Intel has been pushing its upcoming Omni-Path interconnect as a replacement for the popular InfiniBand interconnect that is very popular within high-performance computing. Intel is offering Knights Landing CPUs in configurations with on-package Omni-Path fabric and says that this integration leads to reduced cost, latency, and power consumption relative to discrete solutions.
From a financial perspective, integrating the Omni-Path fabric onto its processors (starting with Xeon Phi, and continuing with the Skylake-based Xeon processors expected to launch in 2017) should be a win for Intel.
Not only should parts with integrated Omni-Path help drive Intel's chip average selling prices up, but should Omni-Path gain significant traction, Intel stands to benefit from the sales of other Omni-Path related components (switches, cables, and so on).
How does Knights Landing perform?
In its Hot Chips presentation, Intel provided a slide showing both performance and performance-per-watt figures of Knights Landing relative to two 14-core Haswell-based Xeon E5-2697 v3 chips:
Source: Intel presentation.
In terms of general-purpose performance as measured by the SPECint_rate_base2006 and SPECfp_rate_base2006 tests, the 36-core Knights Landing chip delivers close to the performance numbers that the Haswell-based Xeon processors do.
In terms of peak floating point performance as well as performance in the given deep learning test, the Knights Landing chip actually pulls ahead of the dual Haswell Xeon E5 chips.
As far as performance per watt goes, the Knights Landing chip seems to roughly match the dual Xeon chips in SPECint_rate_base2006 and is actually slightly ahead in SPECfp_rate_base2006. In the other tests (peak floating point performance and deep learning), Knights Landing delivers substantially better performance per watt than the general purpose Xeon chips.
A major step forward for Xeon Phi
Intel has made it clear that it is very interested in aggressively pursuing the high-performance computing market, and it looks like Knights Landing is a very solid step forward on this front. It'll be interesting to see how it fares in the marketplace when it launches, which should be later this year.
