Microprocessor giant Intel (INTC 3.17%) has long been known for its chip-manufacturing prowess relative to competitors. Its manufacturing technologies have often offered better performance than the competition, and it has usually been able to bring denser technologies -- that is, technologies that allow chip designers to pack more functionality into a given area -- to the market sooner than its competitors.
However, in recent years, Intel's chip manufacturing peers Taiwan Semiconductor Manufacturing Company (TSM +1.50%) and Samsung (NASDAQOTH: SSNLF) have been working to try to narrow the gap.
During the next couple of years, Intel is certainly going to face something of a public relations/perception nightmare as its chip-manufacturing peers transition to technologies that they refer to as "7-nanometer" -- usually smaller is better -- around the time when Intel will be in production on a technology that it calls "10-nanometer." Although there's more to a chip-manufacturing technology than density, it's a relevant metric that has a direct impact on the capabilities that these companies can, cost-effectively, put into their chip designs.
A question that's worth pondering, then, is the following: Will Intel be able to maintain chip-area leadership with its 10-nanometer technology even as competitors transition to their "7-nanometer" technologies? I think the answer to that is "yes." Here's why.
Comparing TSMC's public statements with Intel's
I consider TSMC to be Intel's fiercest and most capable competitor. It's the world's most successful contract chip manufacturer, and over the last several generations, it has executed brilliantly in ramping new manufacturing technologies into production in support of Apple's (AAPL +0.61%) A-series processors.
In contrast, Samsung has lost Apple's business, and is even reportedly actively shifting focus away from contract chip manufacturing in favor of display manufacturing. In light of this, I think the most interesting discussion is one in which we look at Intel's and TSMC's public statements head-to-head.
A metric that Intel uses (publicly) to compare the relative densities of two manufacturing technologies is gate pitch multiplied by cell height. (A visual representation can be found below.)
Image source: Intel.
Intel says that, using this metric, its 10-nanometer technology offers "close to a full generation lead in logic density," as illustrated in the slide below:
Image source: Intel.
Intel also claims that its 10-nanometer technology provides better than its historic 0.46 times scaling factor relative to its 14-nanometer technology, though the chipmaker doesn't specify by how much.
In the table below, I show the gate pitch multiplied by minimum metal pitch -- a similar metric that Intel and others have used in the past in place of gate pitch multiplied by cell height -- for several Intel and TSMC technologies, as well as my projections. This is based on Intel's and TSMC's public statements for what future technologies will bring:
|
Intel |
TSMC | |
|---|---|---|
|
14nm/16nm |
3640 |
5760 |
|
10nm |
<1674 |
~2880 |
|
7nm |
N/A |
~1766 |
Data sources: Intel and TSMC.
At the 14/16-nanometer generation, Intel had a clear lead over TSMC in terms of density. TSMC says (via EETimes) that it will go into mass production on its 10-nanometer technology by the end of the year, and that it will provide a 50% area reduction compared to its 16-nanometer technology. TSMC's 10-nanometer technology should be superior to Intel's 14-nanometer technology in terms of chip area, and it should be in mass production before Intel's 10-nanometer technology.
At 10 nanometers, Intel should see a scaling factor of something smaller than 0.46 times, per its own statements, resulting in the <1674 figure given in the table above. According to EETimes, TSMC claims that its 7-nanometer technology will offer a 1.63 times the density of its 10-nanometer technology -- an implied scaling factor of ~0.613 times.
Intel should have a slight area lead
Based on the analysis above, Intel's 10-nanometer technology should have a slight area lead over TSMC's 7-nanometer technology. What this means is that Intel's marketing claims that it's almost a generation ahead of TSMC are virtually worthless because TSMC's 10-nanometer technology should be in mass production before Intel's.
In fact, in terms of timeline, TSMC's 7-nanometer technology is expected to go into mass production in the first quarter of 2018 -- approximately two quarters after Intel begins mass production of its 10-nanometer technology. (Intel's first 10-nanometer chips should go on sale in the fourth quarter of 2017 according to leaks, implying mass production starting in the third quarter of 2017).
The reality is that, in terms of chip area scaling, Intel is likely to have a roughly six-month lead over TSMC. This, in the scheme of how long these technologies are expected to remain leading edge, is just not all that long.
The good news for Intel is that, contrary to the marketing labels that TSMC (and other contract chip manufacturers) assign to their technologies, it won't actually fall behind its competition in terms of chip area scaling. The days of Intel having a substantial leadership position in this metric, though, are likely long gone.
