Longtime Intel (INTC +0.78%) CFO Stacy Smith recently transitioned into a new role; he's now the "executive vice president leading manufacturing, operations and sales" for the company, according to his biography on Intel's website.
Image source: Intel.
Smith recently presented at the Credit Suisse Technology Media and Telecom conference and offered a lot of good insights into the company's current business and long-term strategy -- it's well worth a listen.
During the conference, analyst John Pitzer asked Smith the following question: "I think there's a concern out there that as you guys have toggled from tock-tock to now what looks like tick-tock-tock that perhaps your relative lead on Moore's Law has somewhat diminished. How, how do you answer that question?"
Let's look at what Smith had to say.
Claims of significant leadership
Smith began by saying that "in terms of [Intel's] relative Moore's Law leadership, as measured by, again, cost per transistor, it's -- from everything that we can see, it is still significant; it is still a generation lead over anybody else."
To understand this statement, it's important to understand what Smith means by cost per transistor. A chip is made up of a bunch of extremely small elements known as transistors. Broadly speaking, the more functionality a company wants to add -- processor cores, graphics, and so on -- the more transistors are required.
Chipmakers try to reduce the area a transistor takes up at a rate faster than wafer costs grow. Smaller transistors require more complex manufacturing techniques, so the cost per unit area goes up. But if a chip manufacturer pulls it off, the cost per transistor goes down.
Intel's argument is that its chip manufacturing technologies allow its designers to cram more of those transistors into a given chip area than competing technologies can, translating into lower chip costs relative to its competition.
One metric Intel has used in the past to compare the relative densities of its manufacturing technologies with those of competing technologies is the product of a technology's minimum metal pitch with its gate pitch.
Image source: Intel.
Does that claim hold up?
Intel's 14-nanometer technology featured a minimum metal pitch of 52 nanometers and a gate pitch of 70 nanometers. Its next-generation 10-nanometer manufacturing technology is expected to have a gate pitch of 54 nanometers. Intel indicated back in August that it scaled the minimum metal pitch of its 10-nanometer technology relative to that of its 14-nanometer technology at a faster rate than it did the gate pitch between the generations.
That'd put the minimum metal pitch at somewhere below 40 nanometers. My guess is that it will be 36 nanometers: Scale the product of Intel's 14-nanometer gate and minimum metal pitches by 0.51, and divide by 54.
Intel's 10-nanometer technology is expected to go into mass production in the second half of 2017. The fiercest competitor that Intel's 10-nanometer technology is likely to have is Taiwan Semiconductor Manufacturing Company's (TSM 1.03%) 7-nanometer technology. TSMC has not yet disclosed the gate pitch of its 7-nanometer technology, but it did disclose that it would feature a minimum metal pitch of 40 nanometers.
TSMC did say in its paper describing its 7-nanometer technology that chip area scaling of that technology relative to its 16-nanometer technology, which featured a minimum metal pitch of 64 nanometers and gate pitch of 90 nanometers, was approximately 0.43.
So if we assume that the product of the gate and minimum metal pitches scales by a factor of 0.43 in going from TSMC's 16-nanometer technology to its 7-nanometer technology, then the product of those two figures should be around 2,476 for the 7-nanometer technology. Dividing that by 40, the minimum metal pitch, yields an estimated gate pitch of approximately 62 nanometers.
Based on this metric, it looks as though Intel will get into production a couple of quarters earlier than TSMC will -- the third quarter of 2017 for Intel's 10-nanometer; the first quarter of 2018 for TSMC's 7-nanometer. Intel's technology should also be a little denser than TSMC's, at around 0.785 times the chip area, going by my estimate.
I don't know that I'd call this a "full-generation lead," considering that a "generation" is two to three years long these days, but Intel does indeed appear to have a lead.
