Earlier this week, Samsung (NASDAQOTH:SSNLF) reportedly showed off its 10-nanometer chip manufacturing technology. It is not clear what the company built in said technology (the reports are quite vague), but some of the headlines are implying that what Samsung presented puts it "ahead" of Intel (NASDAQ:INTC).
I, for one, do not buy those claims.
What's in a name?
When people talk about a semiconductor manufacturing technology, they tend to use what is known as the "node label" -- such as 28-nanometer, 20-nanometer, and 14/16-nanometer. But they are really just that: labels.
What really matters is the kind of performance and power the process can deliver and how much functionality can be packed into a given area footprint.
Major semiconductor companies routinely present papers at popular industry forums describing the key features of their latest chip manufacturing technology. Interestingly enough, Samsung actually published a paper at the VLSI Symposium describing some of the key features of its 10-nanometer process.
Although Samsung did not talk about transistor performance and power, it did reveal two metrics useful for comparing the "density" of the process: minimum metal pitch and gate pitch.
It is pretty close to Intel 14-nanometer
Intel disclosed that its 14-nanometer technology features a minimum metal pitch that comes in at 52 nanometers and a gate pitch of 70 nanometers. The Samsung 10-nanometer process features a 48-nanometer minimum metal pitch and 64-nanometer gate pitch.
If we accept the metric minimum metal pitch multiplied by gate pitch as a useful proxy for density (it seems to be pretty widely used these days), then a design implemented in the Samsung process should take up 85% of the area required by the same design in an Intel 14-nanometer process.
In other words, the Samsung 10-nanometer technology seems to be ahead of what Intel is delivering with its 14-nanometer technology, but obviously Intel 14-nanometer products have been on shelves since late last year, while Samsung 10-nanometer technology may not be available for a few years.
Using SRAM bit-cell sizes: a sanity check
A good way to try to compare the relative densities of two processes is to look at two comparable designs. One popular structure is an SRAM bit-cell. It is well known that SRAM can be a significant part of many modern chip designs and is generally accepted as a reasonable measure of the kind of density that can be achieved in a given process.
Samsung reported building a 0.053 square micrometer SRAM bit cell in the 10-nanometer process described. This would seem to be directly comparable to the 0.0588 square micrometer SRAM bit-cell size reported by Intel in its 14-nanometer disclosures. These numbers roughly match the gate pitch-by-minimum metal-pitch comparisons (the Samsung SRAM bit cell takes up 90% of the area that the Intel 14-nanometer uses), serving as a good "sanity check" for the preceding analysis.
Cutting through the marketing smokescreen
I firmly believe that Samsung "10-nanometer" technology looks quite a bit more like Intel 14-nanometer technology than what I would expect from Intel 10-nanometer technology. Although Samsung and Intel may go into production on their respective 10-nanometer technologies at roughly the same time, I think that any "parity" that Samsung reaches with Intel here will be in name only.