A wafer of server chips. Image credit: Intel.
I have written several columns discussing my concerns around microprocessor giant Intel's (INTC +2.59%) standing in the world of leading-edge logic manufacturing technology. In particular, I have been concerned that the company, which has long led its competitors in terms of performance and, arguably, transistor density, stands to lose this lead and potentially even fall behind foundry giant TSMC (TSM 0.33%).
During Intel's most recent shareholder meeting, I brought up my concerns around this. However, CEO Brian Krzanich assured investors that Intel's 14-nanometer technology will "still outperform any of the other technologies that'll be introduced in the next several years."
Although Krzanich and the individuals running Intel's chip manufacturing division likely have more insight into the matter than most people on the outside will, I don't know if I can accept it without some hard data. Here's why.
The transistor performance question
At the 22-nanometer technology node, Intel brought into high volume manufacturing a new transistor structure known as a FinFET. The details aren't important, but the bottom line is that FinFETs allow for better performance at lower power consumption than traditional "planar" transistors.
Now, one thing for investors to realize is that not all FinFETs are created equally. When Intel first disclosed details of its 14-nanometer technology, it said that it made the silicon "fins" in its 14-nanometer technology both narrower and taller than those used in its 22-nanometer technology.
Image credit: Intel.
The main point here is that taller and thinner fins allow for better transistor performance -- allowing for more performance at a given level of power consumption or lower power consumption at a fixed level of performance.
Intel disclosed in late 2014 that in its 14-nanometer process, the "fins" are 8nm wide and 42nm tall.
In a presentation from electronic design automation tool and IP vendor Synopsys (SNPS 0.07%) earlier this year, the company showed a very interesting slide:
Image credit: Synopsys.
According to Synopsys, 14/16-nanometer processes used a fin width of 9-nanometer and fin height of 42-nanometer. I doubt that Synopsys is referring to just Intel here (since Intel doesn't even have a "16-nanometer" process), so it stands to reason that Intel wasn't the only company with a 42-nanometer fin height at the 14/16-nanometer generation.
What's more interesting is that Synopsys says that at the 10-nanometer node, chip manufacturers will move to fin heights of approximately 50 nanometers and widths of 8 nanometers. And, at 7-nanometers, fin height goes above 50 nanometers.
Intel needs to flesh out its assertion a bit more
At this point, I think it's worth taking Krzanich's claim about Intel's 14-nanometer technology offering superior performance to "other technologies that'll be introduced over the next several years" with a healthy dose of skepticism.
Assuming that Intel dedicates a whole presentation to discussing transistor technology later this year at its investor meeting, there's actually a really easy way for the company to "prove" its claim: show some data.
In particular, Intel could show performance data for its 14-nanometer transistors and compare it to measured transistor performance from competing 14/16-nanometer technologies. Given that TSMC has publicly discussed the kinds of performance improvements it expects from its 10-nanometer technology (up to 18% higher speeds or 40% less power consumption, per EETimes), it shouldn't be hard for Intel to give its own internal projections of TSMC's 10-nanometer performance (and even 7-nanometer performance) relative to its 14-nanometer technology.
