At its annual developer forum, microprocessor giant Intel (NASDAQ:INTC) disclosed quite a lot of information about its current and future chip manufacturing technologies, something that was sorely needed after a long stretch of essentially radio silence.
There is a lot of ground to cover here as the presentation that the company gave was packed to the brim with goodies. Let's get to it.
Say hello to 14+
One topic that Intel talked about was the development of "derivative technologies" based on current manufacturing technologies. These derivative technologies, according to Intel, are "becoming more common to enhance performance and/or expand feature set."
The first such derivative technology that Intel is announcing (or, at the very least, bothering to brand for investors' sake) is 14+. This is a technology that includes enhancements to both the transistor as well as the metal stack to yield a performance improvement of 12%.
This process is what the company's upcoming Kaby Lake family of processors as well as, I assume, the company's second generation of 14-nanometer server processors slated for launch in 2017, will be built on.
Three waves of 10-nanometer
Intel says that there will be three waves of its future 10-nanometer technology: 10, 10+, and 10++. These, the company says, will "support multiple new leading-edge products."
This means that even though Intel will be "stuck" on its 10-nanometer technology for three product generations, the company should be able to wring out additional manufacturing-related performance enhancements on top of product-level architectural improvements.
Intel claims significant density advantage over competition
One metric that Intel has talked quite a lot about is the logic area density of its manufacturing technologies relative to competing technologies from Taiwan Semiconductor Manufacturing Corporation (NYSE:TSM) and Samsung Electronics (OTC:SSNLF).
The idea is that the more tightly a company can pack transistors (what chips are made of), the more features and functionality it can cram into a fixed chip area.
Here's the slide that Intel showed comparing its technologies with those from its competition:
According to the company, its 14-nanometer technology -- using the metric of transistor gate pitch multiplied by logic cell height -- is a little less dense than competitors' upcoming 10-nanometer manufacturing technologies. Intel's own 10-nanometer technology, per this comparison, will be dramatically ahead of the competition in this metric (though it's worth noting that Intel's 10-nanometer technology should come a bit later than the competitions').
Although I believe that Intel will be able to maintain a solid transistor density lead over Samsung, the competitive picture vis-à-vis TSMC is a little less clear. Though it is true that Intel's 10-nanometer should be quite a bit denser than TSMC's 10-nanometer, TSMC has indicated that it will transition to its 7-nanometer technology in the first half of 2018.
TSMC claims that its 7-nanometer technology will bring both performance and area enhancements relative to 10-nanometer, so I expect the gap, at the very least with respect to transistor area, to narrow relative to Intel's 10-nanometer technology. Whether TSMC closes the gap or not, remains to be seen.
I suspect, though, that any sustained advantage that Intel will be able to build over TSMC won't necessarily be in terms of transistor area but, instead, in transistor performance as the company iterates through its 10, 10+, and 10++ technologies.
What does this mean for the business?
At the end of the day, it's Intel's job to build compelling products for the various markets that it serves. Yearly performance improvements in manufacturing technology should allow the company to release better and faster products each year, allowing it to gain share in new areas (such as the Internet of Things and networking) while defending its position in areas where it's already strong (personal computers, servers).