A while back, KGI Securities analyst Ming-Chi Kuo predicted that Taiwan Semiconductor Manufacturing Company (NYSE:TSM) would manufacture Apple's (NASDAQ:AAPL) A10X Fusion processor, the chip that powers the newly released 10.5-inch iPad Pro and updated 12.9-inch iPad Pro.

Moreover, Kuo predicted that the A10X Fusion processor would be built using TSMC's 10-nanometer manufacturing technology, rather than the contract chip manufacturing giant's older 16-nanometer+ technology.

Apple's 10.5-inch iPad Pro.

Image source: Apple.

Per a new teardown report from chip specialists TechInsights, it would seem that -- as is often the case -- Kuo was dead-on.

A lot of chip in a small area

The A10X Fusion appears to be the first commercially available chip manufactured in TSMC's 10-nanometer technology, though other chips built using the technology -- like Apple's upcoming A11 Fusion chip for this fall's iPhone models -- should also be on the way.

The A10X Fusion, according to TechInsights, is a rather small chip. While the A9X measured in at a whopping 143.9 square millimeters (all measurement data from TechInsights), the A10X comes in at just 96.4 square millimeters.

That area reduction (even with substantial new features added to the chip) is, unsurprisingly, because TSMC's 10-nanometer technology represents a full-generation area reduction from the various 20-nanometer/16-nanometer technologies that Apple used to build the A9, A9X, and A10 Fusion.

Remember that Apple's A8 and A8X were built using TSMC's 20-nanometer technology, the A9 was built using either Samsung's (NASDAQOTH:SSNLF) 14-nanometer tech or TSMC's 16-nanometer technology (depending on the variant), and both the A9X and the A10 Fusion were built using TSMC's 16-nanometer technology.

TSMC's 16-nanometer technology didn't really offer much of an area reduction relative to its 20-nanometer technology; most of the improvements came in the form of performance enhancements thanks to the adoption of a new transistor structure known as a fin field-effect transistor, or finFET.

What does this tell us about the A11 Fusion?

I suspect that the A10X Fusion was designed as a relatively low-risk "pipe cleaner" part for TSMC's 10-nanometer manufacturing technology ahead of the ramp-up of production of the A11 Fusion chip that'll power this year's iPhone models.

Thus, I expect that the A11 Fusion will be larger and more complex to manufacture than the A10X Fusion is, but in return, Apple should be able to deliver some seriously impressive capabilities in its next iPhone.

Here are some of my expectations (to be clear, there are educated guesses, not facts) around how various parts of the A11 Fusion will compare with the A10X Fusion:

  • The A11 Fusion will stay with a 2+2 core configuration; that is, two high-performance cores and two high-efficiency cores. The A10X Fusion is in a 3+3 configuration, but I expect that the cores inside of the A11 Fusion (both the high-performance cores and the high-efficiency ones) will be larger, more power-efficient, and ultimately faster than the ones in the A10X Fusion.
  • I expect that Apple will use the dramatic transistor area reduction in going from 20-nanometer/16-nanometer class technologies to the 10-nanometer technology to beef up the size of the graphics processor in the A11 Fusion compared to the one used in the A10 Fusion. I'm expecting an eight- to 10-core graphics processor, up from the six-core graphics processor found in the A10 Fusion and below the 12-cores found in the A10X Fusion.
  • I expect that, in support of the iPhone 8's dramatically enhanced camera/imaging/3D sensing capabilities, Apple will introduce an overhauled, next-generation Image Signal Processor in the A11 Fusion compared to the one used in the A10/A10X Fusion, which should add transistors and, thus, chip area.
  • I could see Apple increasing the sizes of the on-chip cache memories on the A11 Fusion compared to that on the A10 Fusion as well.

All told, if I had to take a shot in the dark right now, I'd bet on the A11 Fusion measuring in at around 110-120 square millimeters, or a bit larger than the A10X Fusion, making it a bit more expensive to manufacture than the A10X (something that should benefit TSMC).