Contract chip manufacturing giant Taiwan Semiconductor Manufacturing Company (TSM 0.36%) said on its most recent earnings conference call that over the next several years, it intends to spend between $10 billion and $12 billion annually on capital expenditures. TSMC's capital spending has been in that ballpark for the last several years now. 

TSMC also explained that although it intends to keep its capital equipment spending roughly in line with where it has been in recent years, that level of spending should be enough to support the company's annual revenue growth target of between 5% and 10%.

A wafer of processors.

Image source: Intel.

At first glance, this might be a little confusing. After all, if TSMC expects to ship more product and if each new generation of manufacturing technology becomes increasingly capital intensive, then shouldn't the company be spending more on capital equipment to support its expected demand increases?

Here's why that's not the case, according to the company. 

Productivity enhancements boost effective capacity

TSMC CFO Lora Ho said that the business can wring more out of its preexisting capacity "through productivity improvements." 

"That is, for the same tools, the output can increase every year through our engineering efforts and innovations," she said. "This way, without spending fresh [capital expenditures], we are able to grow capacity to support growth."

Ho then went on to say that these productivity improvements are good for a mid-single-digit improvement in effective manufacturing capacity growth each year. 

What does TSMC mean by productivity improvements?

To understand what TSMC means by productivity enhancements, it's important to have a little background on chip manufacturing technology. 

The effective capacity for a given manufacturing technology is heavily influenced by two major factors: yield rates and cycle times. 

Yield rate is the percentage of the chips produced on a silicon wafer that are salable. Yield rate is heavily influenced by the average number of defects found on a fully processed wafer -- the lower the average number of defects, the higher the percentage of the chips produced that will work. The higher the yield rate of a given manufacturing technology, the fewer the wafers that need to be processed to produce a certain number of chips, increasing effective capacity. 

The second measure, cycle time, refers to how long it takes to process a wafer from start to finish. Cycle time tends to grow with each new manufacturing technology since newer technologies are more complex and require more processing steps to complete. I wouldn't be surprised, then, if part of TSMC's "engineering efforts and innovations" involved a shortening of cycle times for many of its technologies to boost effective capacity. 

Business implications

From a financial perspective, these productivity improvements mean that TSMC needs to spend less on capital expenditures to improve its business. Lower capital expenditures today imply lower depreciation costs tomorrow, which should ultimately translate into lower manufacturing costs per wafer.

Those lower manufacturing costs per wafer can be applied in one of two ways: gross profit margin improvement at a given wafer selling price or wafer price reductions at roughly the same profit margins. 

The former would allow TSMC to improve its profitability at fixed volume, while the latter could potentially allow the company to be more effective both at defending its current high foundry market share (IC Insights says that TSMC captured more than half of total contract chip manufacturing industry revenue in 2017) and in trying to expand its share.