When Intel (INTC +1.07%) gave its "analyst day" presentation on Nov. 21, 2013, Intel showed a chart that confirmed the company means pretty serious business in both transistor leadership and metal stack density leadership. Indeed, Intel admitted that its 22-nanometer process was roughly on par with TSMC's (TSM +1.40%) 28-nanometer process with respect to density, though it offered a significant performance advantage. However, at 14-nanometers, Intel claims that the game changes.
Intel's claim -- a focus on the metal stack
When it comes to semiconductor manufacturing technology, there are two major components:
- Front-End-Of-Line, or FEOL, which refers to the actual transistors from which the semiconductor devices are built
- Back-End-Of-Line, or BEOL, which refers to where the devices (transistors and other components) are connected together via metal wires.
The interesting thing here is that, as the FEOL gets smaller, transistors typically offer better performance. This is widely considered the "magic" of Moore's Law. However, metal wires have a tendency to offer worse performance when they are made smaller, so an "easy" solution -- particularly for designers interested more in performance than density -- is simply to be less aggressive in scaling the BEOL than the FEOL.
So, take a look at the following slide:
Source: Intel
Intel is claiming that, based on TSMC's claim that its metal stack at 16FF will be carried over from the 20-nanometer generation, its 14-nanometer process will offer a roughly 35% density edge on TSMC's 16FF process. Note that Intel appears to be using the minimum metal pitch as a proxy for density.
TSMC's dubious claim
On its most recent earnings call, TSMC gave the following explanation for why Intel's chart was "highly misleading":
Therefore, we leverage the volume experience in the volume production this year to be able to immediately go down to the 16 volume production next year, within 1 year, and this transistor performance and innovative layout methodology can improve the chip size by about 15%. This is because the driving of the transistor is much stronger so that you don't need such a big area to deliver the same driving circuitry.
In essence, TSMC is claiming that, because the chip designers can trade off performance for density with a density-focused layout, this allows them to claim a "15% density advantage" over its 20-nanometer process, even with the same metal stack. Unfortunately, this doesn't pass the smell test because Intel, with its own designs, could do the exact same thing and have a denser metal stack, thereby nullifying any density "advantage" that TSMC can garner from an improved layout methodology. This -- not Intel's claims -- is what appears to be misleading here.
Foolish bottom line
TSMC is trying to convince investors that it is keeping up with Intel with regard to transistor technology, but the truth is that Intel has been ahead for many generations. Sure, TSMC is increasing its investments here, but so is Intel. Further, since Intel is an integrated device manufacturer, it can co-optimize the process and design in ways that a fabless/foundry relationships would have a tough time emulating.
In addition, TSMC is claiming that customers will begin "taping out" designs during 2014 on the 16FF process. This is a dead giveaway that Intel is still ahead, given that it has demonstrated fully functional designs built on its 14-nanometer process. This means that tape-out happened quite a while ago, and with Intel's roadmap also suggesting that a 14-nanometer mobile SoC is on track for late 2014, Intel is very likely ahead in both high performance CPU and low power SoC flavors of its process.
