On August 11, Intel (NASDAQ:INTC) held an event detailing its next generation 14-nanometer manufacturing technology as well as the first product that it plans to build on it. There's been a lot of hype from many chipmakers – including Intel and its rivals Samsung (NASDAQOTH:SSNLF) and Taiwan Semiconductor (NYSE:TSM) – about their respective 14-nanometer and 16-nanometer technologies, but with Intel's recent disclosures, we can finally get a sense of the competitive landscape.

An important caveat to consider
Trying to judge the competitiveness of a semiconductor manufacturing process is difficult and often analysts and investors make the mistake of confounding the performance and density characteristics of a process with the end products that come out of the chute.

Note that Intel's 22-nanometer FinFET process offered higher performance and lower power relative to its 28-nanometer planar peers. In fact, electronic design automation tool vendor Synopsys, noted in a 2012 blog post that, "one major design optimization alternative designers have in FinFETs, as compared to planar technology, is much better performance at the same power budget, or equal performance at a much lower power budget."

However, even with a much "better" process, Intel's 22-nanometer mobile system-on-chip products failed in a number of key ways to be competitive with their 28-nanometer contemporaries due to execution issues at the product level.

In other words, process is an enabler, but it's not everything.

With that caveat in mind, let's take a closer look at how the 14/16-nanometer processes from Intel, Samsung, and Taiwan Semiconductor compare.

Talk density to me
In the table below, the relevant transistor and metal pitch characteristics are listed from published specifications from each of the three vendors' processes:


Intel 14-nanometer

TSMC 16-nanometer

Samsung 14-nanometer

Gate pitch (nanometers)




Minimum metal pitch (nanometers)




Fin pitch (nanometers)




6T SRAM cell size (square micrometers)




Estimated minimum logic cell size (square nanometers) – calculated by (gate pitch * minimum metal)




Source: Intel, TSMC, Samsung data.

The reason that the density of a chip is so important is very much due to economics. The wafers that these chips are built on are of a fixed size, and the more functionality that a company can pack in a given area for a given cost, the more competitive that company's chips will be.

To understand the chart above, it's important to define some of these terms. Hans de Vries, who runs the site Chip Architect, notes , "the contacted gate pitch determines the minimum distance at which you can put two transistors [the building blocks of chips] together."

He further adds, "more important however for dense routing is the metal interconnect which wires all the transistors together in actual circuits."

Intel takes this a step further in its own presentation and asserts that the area of a logic circuit can be estimated by minimum metal pitch multiplied by gate pitch. While this is likely a crude approximation at best, such estimates would suggest that Intel's 14-nanometer process is a 27% shrink from Samsung's 14-nanometer and about a 37% shrink from Taiwan Semiconductor's 16-nanometer process. 

However, do keep in mind that Intel's reported SRAM cell size does not exhibit a density advantage in-line with Intel's claimed logic density advantage. This means that in real-world processors (which often incorporate significant amounts of SRAM as cache memory -- see the image below), Intel's chip-level density advantage is likely to be lower than the theoretical logic density advantage calculated above.

This is Intel's Sandy Bridge EP. It has lots of cache. Source: Intel. 

Time to market and performance
Intel's first 14-nanometer product -- Core M -- began initial production during the first quarter of 2014 and was qualified in the second quarter of 2014, according to statements that Intel's executives made on recent confernece calls. Further, Intel management expects subsequent products are likely set to hit the market during 2015.

TSMC, on the other hand, claims that its 16-nanometer process will begin volume production in late 2015, which means that broad product availability may not be until early 2016. Samsung, on the other hand, claims that it will be going into mass production on its 14-nanometer process by the end of 2014, with its in-house processors ramping over the first half of 2015 and foundry customers' designs ramping over the second half of 2015.

It is not clear when these Samsung-designed chips will end up shipping to end-users (according to Tom's Hardware, Samsung's first 20-nanometer applications processors will begin to show up in customer devices by the fourth quarter of 2014 in the Galaxy Alpha and, likely, the Galaxy Note 4), but it does look as though Intel has a time-to-market edge on both foundries (though a much wider lead against TSMC than against Samsung if the latter delivers on schedule).

The final point is actual transistor performance. TSMC has published the performance characteristics of its 16-nanometer process, but Intel won't publish its 14-nanometer transistor performance numbers until the Intel Developer Forum in September. To my knowledge, Samsung has not published performance characteristics of its 14-nanometer process.

Foolish bottom line
Intel's 14-nanometer process is denser and in production before competing processes; this is an achievement to not be taken lightly. While Intel still has yet to prove that its chip teams can use this manufacturing technology to put together compelling mobile products, it'll be interesting to see if the company's 2015 mobile product line can do the trick.