Back in Sept. 2014, Intel (INTC 4.09%) announced a new product category known as Core M. According to the company, Core M chips are best suited for very thin and light devices where low power consumption is a must. The company's current Core M chips are rated at 4.5 watt "thermal design power," and Intel claims that these chips enable fanless 2-in-1 systems that are under 9 millimeters thick.
According to CPU World, the next-generation Core M processor based on Intel's Skylake architecture is set to raise (or is it lower?) the bar by bringing the rated thermal design power to just 4 watts, an 11% reduction. Additionally, with Skylake Intel is bringing a redesigned graphics and media subsystem and faster CPUs to boot.
Given that Skylake will be built on the same 14-nanometer manufacturing technology that today's Broadwell-based Core M processor is, the question is: how will Intel achieve a performance increase generation-on-generation while shrinking power consumption?
An improved architecture
While Intel talks a lot about the quality and performance of its transistors, investors should keep in mind that the folks responsible for the architecture and implementation of the chips are critical to the competitiveness of a chip.
With Skylake, the CPU is likely to be getting a massive overhaul from Haswell/Broadwell. Remember, Intel has in place what is known as the "tick tock" development methodology. Broadwell was a "tick," meaning it is a polished-up Haswell. Skylake is a "tock," meaning that the architecture will be improved/modified in more significant ways.
The graphics and media are also looking like they will see a huge boost in Skylake. In tasks such as video playback, the Gen. 9 graphics architecture found on Skylake will reportedly feature hardware support for new codecs in hardware. This should lower power consumption for intensive tasks such as 4K video playback over the Broadwell chip.
However, while I'm excited about the architectural enhancements in the main processing units of the chip, there's another big opportunity that Intel has to lower power: in the Platform Controller Hub, or PCH.
Moving the PCH to the 22-nanometer node should be good for power reduction
Take a look at the following picture of the Core M chip:
Source: Intel.
Notice that there are two dies on the same package? The long one on the top is where the CPU cores, graphics, media engine, and so on are located. The smaller one on the bottom is called the Platform Controller Hub, and this contains audio processing capability, PCI Express connectivity, USB, and other functionality.
The PCH is built on the now-ancient 32-nanometer manufacturing technology, similar to the PCH found on last year's Haswell chips. Intel claims that the PCH on Broadwell, despite being built on the same 32-nanometer process as the prior design, sees a 25% reduction in idle power and a 20% reduction in active power (i.e. when it's doing stuff).
It has been widely discussed that if Intel moves this block from the 32-nanometer process to its 22-nanometer FinFET manufacturing technology, then it could see a substantial reduction in idle and active power consumption. This could be a critical enabler to that 0.5 watt reduction in thermal design power from Broadwell Core M to Skylake Core M.
In addition to making a better product, there's another business reason Intel might be eager to move its PCH chips to 22-nanometers.
This is a good way to keep those 22-nanometer factories full
As Intel brings online its new 14-nanometer fabs, and as those fabs take over the majority of the PC chip volume from whatever 22-nanometer capacity is in place, Intel will need to fill that 22-nanometer capacity with something.
Each Skylake processor, whether it be Core M or Core i-series, will need an accompanying PCH. These PCH chips, though not as large as full-blown processors, still use up quite a bit of die area. Moving these to 22-nanometers will help keep whatever 22-nanometer capacity hasn't been rolled forward to future technologies utilized.
As CPU World has reported previously, Intel also plans to make more liberal use of on-package eDRAM in its Ultrabook, high-end notebook, and even some desktop Skylake parts. This on-package eDRAM not only helps improve graphics performance and drive average selling prices up, but it -- just like the PCH chips -- will help keep those 22-nanometer factories at high utilization rates.
