About a year ago, Intel (NASDAQ:INTC) publicly discussed some details of its 14-nanometer manufacturing technology. The process, according to the company, offers significant area scaling and efficiency enhancements relative to its prior-generation 22-nanometer process.
At the time, the company showed the following slide:
Although Intel didn't provide a scale by which to precisely compare the yields of the aforementioned Broadwell chip and the corresponding 22-nanometer chip, it's clear that Intel had a much easier time getting its 22-nanometer lead product yields up to speed than it did with its 14-nanometer lead product.
This stuff, frankly, is getting really tough.
What is interesting, though -- and something that I hadn't thought of previously -- is that even if the yields at the chip level between the lead 14-nanometer product and the 22-nanometer product weren't all that different, there is another factor to take into account in comparing the two: die sizes.
Intel talked about yields, not defect density
It is telling that the company talked about chip level yields rather than the metric that it has used in previous process technology disclosures: defect density.
In a nutshell, "yields" in the slide mentioned above refer to what percentage of the chips on a given semiconductor wafer actually work. "Defect density," on the other hand, is a measure of the average number of chip-killing defects per unit of area.
For a given defect density, smaller chip sizes will lead to a greater percentage of "good" chips on a given silicon wafer. In this document, which discusses semiconductor yields and yield management, the authors provide a very good diagram illustrating why smaller chip sizes tend to lead to better yields for a given defect density:
Armed with this knowledge, it's not hard to understand why the yield trend/forecast that Intel gave with respect to its lead 14-nanometer Broadwell product was not as impressive as it might have originally seemed.
Indeed, the 22-nanometer lead product that Intel is referring to is the 2 CPU core + GT2 Haswell-U processor. The die size of this chip measured in at 130 square millimeters; in contrast, the Broadwell-Y chip mentioned in the Intel slide measures in at just 82 square millimeters.
The fact that, at the time of product qualification, that Intel wasn't able to get the yields of an 82-square-millimeter chip to even just match those of a much larger 22-nanometer chip speaks volumes to the challenge that Intel had in getting 14-nanometer into economically viable, high volume manufacturing.
What does this mean for investors?
At Intel's most recent investor meeting, the company showed the following chip cost curves for several product generations:
According to Intel, the cost to manufacture the 82 square millimeter 14-nanometer Broadwell-Y chip will come in slightly below where the 130 square millimeter 22-nanometer Haswell chip was at the same point in its ramp-up by the third quarter of 2015.
For the sake of this analysis, let's assume that Intel is predicting equal cost structures. What does this imply about the kinds of yield improvements that Intel is expecting at that point?
Well, Intel has said that wafer costs in going from the 22-nanometer generation to the 14-nanometer generation go up by about 30%.
The implied cost per chip is given by the following equation:
- Chip cost = wafer cost/number of good dies
Let's now set up our two relevant equations:
- Haswell cost = 22-nanometer wafer cost/number of good Haswell dies
- Broadwell cost = 14-nanometer wafer cost/number of good Broadwell dies
We know that in this case, the 14-nanometer wafer cost is 30% greater than the 22-nanometer wafer cost. We also know that we want to set the Haswell cost and Broadwell cost equal to each other.
Using basic algebra, it's clear that Intel expects that by the third quarter, it will be able to get 30% more good Broadwell chips from a wafer than it could get from a Haswell wafer.
First, to get an idea of the total number of dies Intel should be able to get from wafers of Haswell and Broadwell chips, respectively, I used Silicon Edge's dies-per-wafer calculator and rough estimates of the dimensions of the two chips from published die photos to perform this calculation.
I calculated 454 total dies from the Haswell wafer and 727 total dies dies from the Broadwell wafer.
Given that Intel should be able to get 60% more chips from a Broadwell wafer than from a Haswell wafer, and given that it is expecting to get only 30% more good chips from a given Broadwell wafer than from a Haswell wafer, we can see that Intel still doesn't expect 14-nanometer defect densities to match those of the 22-nanometer process at the same point in its Haswell ramp.
So the 14-nanometer is proving quite the challenge for the chipmaker.