Chip maker Intel (NASDAQ:INTC) recently closed its purchase of programmable logic specialist Altera. The long-term goal of this acquisition is, among other things, to develop server processors with integrated Field Programmable Gate Arrays, or FPGAs.
Such products should afford server customers the flexibility to accelerate specific workloads without needing to purchase or develop separate accelerators, lowering cost and improving power efficiency.
Intel has indicated that such integration will be a multistep process. The first step involves placing a stand-alone FPGA onto the same package as a Xeon processor. After that, the Xeon processor and the FPGA would be fused together onto a single piece of silicon.
According to an article published in The Next Platform, Intel recently disclosed some additional details about its first "co-packaged" Xeon and FPGA chip.
Broadwell based, with Arria 10 FPGA
The co-packaged chip will apparently feature Intel's upcoming Broadwell-EP (said to be in a 15-core configuration) as well as Altera's Arria 10 FPGA. The part is expected to start sampling later this year and will reportedly ship to customers as an "off-roadmap product" in 2017.
The Broadwell CPU complex will be built using Intel's 14-nanometer chip manufacturing technology, while the Arria 10 will be built with TSMC's (NYSE:TSM) 20-nanometer chip manufacturing technology. A TSMC-built FPGA was widely expected, particularly given the development difficulties that Altera/Intel seem to have had with the first Altera-designed and Intel-built high-end FPGA.
Intel probably doesn't expect huge volumes from this, but that's OK
Given that Intel is expecting to sell this part as an "off-roadmap" product, and given that by the time it'll be available in significant quantities, Intel will have transitioned to its next-generation server chip family (Skylake-EP), the company probably isn't expecting to sell these in large quantities.
However, I think the most important thing here is that Intel is laying the groundwork for future mass adoption of these types of parts. According to The Next Platform, Intel is working to build a whole suite of "FPGA libraries." These libraries, per the article, are expected to provide customers with a bunch of pre-designed accelerators to configure the FPGAs with to "help users accelerate their workloads and give developers a platform to start with."
As Intel builds up these libraries, it should become increasingly easy for data center operators to accelerate common workloads. And, over time, those operators could either program the FPGAs with custom-made accelerators or, I'd imagine, pay Intel (or another third party) to develop a custom accelerator or set of accelerators for them.
When will we see a fully integrated part?
It will likely be a while before we see a fully integrated part. It's unlikely that such a part will arrive in the Skylake-EP generation of server chips (1H 2017 to 1H 2018), and the 10-nanometer Cannonlake-EP generation (likely 1H 2018 to 1H 2019) of chips -- which will be socket-compatible with the Skylake-EP family of products -- seems too early as well.
Late 2019 or early 2020 seems reasonable for a fully integrated, single-chip part, but we'll probably know for sure after Intel hosts its investor meeting in November.
In the meantime, though, I wouldn't be surprised to see Intel release additional co-packaged chips based on newer technologies. Things could get quite interesting if Intel is able to put an FPGA built via its 14-nanometer process onto the same package as a server chip manufactured using the company's 10-nanometer process.
Such a product could be substantially more efficient than the upcoming Broadwell/Arria combination, and could deliver enough performance to sell in reasonably high volumes. Certainly a solid "stop gap" on the road to a fully integrated part.