TSMC (NYSE:TSM) is the largest pure-play chip manufacturing company. It doesn't design the chips that get sold into the marketplace, but it produces what are effectively "silicon canvases" to allow the companies that do design said chips to build their products.
The Taiwan-based chip manufacturer hosted its first-quarter earnings call on April 14 and, in addition to talking about its business performance, provided a fairly substantial update on the state of its current and future chip manufacturing technologies.
Let's take a look at what TSMC had to say.
How's 16-nanometer progressing?
TSMC's current leading-edge manufacturing processes are the family of technologies under the "16-nanometer" umbrella. TSMC has two main technologies here: 16-nanometer FinFET+ for higher performance applications and 16FFC for cost-sensitive and very low-power (i.e., Internet of Things) applications.
According to TSMC co-CEO C.C. Wei, the company's 16-nanometer technology continues to ramp with both yield and cycle time (the time it takes for a wafer to go from start to finish) "better than [TSMC's] target."
"Applications in mobile processors, cellular baseband, video game player, PC graphics will contribute significantly to our 16-nanometer shipment[s] this year," Wei said.
Wei also said that this year, the company would start to ship products including Ethernet switches, CPUs, network processors, programmable logic devices, as well as other chips this year.
All told, Wei claims that 16-nanometer will make up more than 20% of the company's wafer revenue in 2016.
InFO packaging technology update
TSMC is expected to go into mass production on a new chip packaging technology that it refers to as "Integrated Fan Out" or InFO this quarter. It is expected that the first product using this technology will be the Apple (NASDAQ:AAPL) A10 chip that will presumably power the iPhone 7/7 Plus.
"Compared to the conventional package, TSMC InFO has advantage in form factor, such as smaller area and a similar thickness," Wei said. He also claims that power consumption of the chip can be reduced by "as much as 20%."
Wei also went on to explain that using InFO, chip designers can integrate multiple chips into a single package (reducing board footprint) while also bringing down chip costs.
10-nanometer and 7-nanometer technologies
TSMC also provided updates on its 10-nanometer and 7-nanometer technologies. The company says that it has already received its first 10-nanometer product tape-out (i.e., a completed design) from a customer, with more tape-outs expected to occur in the "following quarters."
The company says that the majority of the 10-nanometer tape-outs that it's seeing are coming from mobile-focused customers, with the implication that it will be the upcoming 7-nanometer technology that is broadly adopted across various market segments.
These product tape-outs, per TSMC co-CEO Mark Liu, will "drive a sizable demand starting from [the second quarter of] 2017 through 2018."
It's notable that the company has yet to announce that it has commenced "risk production" on its 10-nanometer technology.
Beyond that, TSMC says that its 7-nanometer technology development is "well on track." Liu describes it as a "further extension" of the company's 10-nanometer node, with "more than 60% in logic density gain" as well as between 30% and 40% lower power.
The company expects to see 15 customer tape-outs on the 7-nanometer technology in 2017, with volume production beginning in the first half of 2018.
What does this mean for investors?
It's pretty clear that the breadth and depth of TSMC's process offerings is impressive and that it will be very difficult for other foundries to keep pace. I believe this should allow TSMC to maintain robust gross profit margins in the 50% range out in time with revenue growth outpacing that of the broader semiconductor and foundry markets.