About a year from now, Apple (AAPL 0.52%) is expected to launch its next-generation iPhones. Although we don't know that much about them, one thing is certain: They'll be powered by a new generation of custom-designed Apple A-series applications processors, and they'll almost certainly be built using Taiwan Semiconductor Manufacturing Company's (TSM 2.71%) 7-nanometer technology.
This new technology, TSMC says, promises to deliver significant performance, power consumption, and chip area benefits over the 10-nanometer technology that's being used to manufacture Apple's latest A11 Bionic chips, which power the iPhone 8, iPhone 8 Plus, and iPhone X smartphones.
Software chief Craig Federighi demonstrating Animoji at the September iPhone event. Image source: Apple.
On TSMC's most recent earnings call, company management provided an update on how the development of this technology is progressing.
Let's go over what the executives had to say.
Out of the labs and into the fabs
TSMC co-CEO C.C. Wei said that the company transferred its 7-nanometer manufacturing technology out of research and development and into manufacturing early in the third quarter of this year. This doesn't mean that TSMC is ready to begin mass-producing chips using the technology, but it does mean that the company is in the final stages of the development of the technology.
"Right now, our efforts focus on defect reduction and fine-tuning device performance to prepare for mass production in the first half of 2018," Wei said.
This might not make sense at first, especially if you're unfamiliar with chip industry lingo, so allow me to break it down for you.
Defect reduction
When a wafer of semiconductor chips is produced, the wafer will have a certain number of defects spread out across the wafer. One metric that's used to measure the health of a manufacturing technology is defect density -- the average number of defects per unit area.
If part of a chip happens to be on an area of the wafer that has a defect, then that chip isoften unsuitable for use.
A chip manufacturer like TSMC aims to reduce the defect density inherent to a manufacturing technology for two big reasons. First, chip manufacturing plants are typically filled with enough equipment to build a certain number of chips under certain assumptions about manufacturing yield rate, which is heavily influenced by defect density.
If a chip manufacturer can't get the defect density down to acceptable levels, then its ability to meet demand could be impaired.
It's not just about meeting demand, though. The lower the defect density of a wafer, the more chips can be produced on a wafer, thereby increasing the value of that finished wafer to customers. This can mean higher wafer selling prices and ultimately better profit margins for the chip manufacturer.
Device performance
With each new generation of manufacturing technology, chipmakers aim to increase performance and decrease power consumption. This allows potential customers to build faster, more efficient products than they could using older-generation technologies, which helps motivate customers to use the latest (and most expensive) chip manufacturing technologies available.
Moreover, chip designers often make their technical decisions based on the expected performance of the technology that they're using. If the chip manufacturer misses the mark on performance (or too few of the chips produced can hit the desired performance levels), then this could negatively impact the capabilities and marketability of a chip product, and ultimately the businesses of the chip manufacturer's customers.
