One of the key aspects of chip-manufacturing technology that Intel (INTC +1.14%) has been laser focused on for some time is the density of the transistors, or the building blocks of computer chips. In a world where Intel and the rest of the chip manufacturing world is dealing with an increase in wafer cost, the well-accepted way to get cost per transistor improvements is to improve density at a rate that outpaces the wafer cost increases.
Now, comparing the densities of different manufacturing technologies is often very tricky, particularly as the density of a chip is often dependent on much more than the underlying manufacturing process; chip-level design decisions and targets also play a large role. Nevertheless, a common way for chip companies to compare process densities is through the minimum SRAM bitcell sizes that can be built with those processes.
In its disclosure back in August, Intel noted that the SRAM bitcell size that it was able to achieve with its 14-nanometer process was 0.0588um^2. This was, to my knowledge, the lowest reported SRAM bitcell size for a 14/16-nanometer process which was impressive, but given that Samsung had reported a high-density SRAM bitcell size of 0.064um^2, it wasn't earth-shattering.
After being pointed to a recent piece published in the EETimes which gives additional data, it seems that the number published back in August didn't tell the whole story.
High density cells versus high performance/low power
According to ElectronIQ, Samsung's (NASDAQOTH: SSNLF) 14-nanometer process -- which is widely regarded as the densest non-Intel foundry process -- offers a high-density bitcell size of 0.064um^2 and a high performance bitcell size of 0.080um^2.
Per a report from the EETimes, Intel's high-density 14-nanometer bitcell size weighs in at 0.05um^2, a fair bit smaller than the 0.0588um^2 bitcell size that the lower-power variant comes in at. The table below shows an apples-to-apples comparison of the Samsung 14-nanometer bitcell sizes with the Intel 14-nanometer bitcell sizes:
|
High-density bitcell (um^2) |
High-performance/low-power bitcell (um^2) | |
|---|---|---|
|
Intel 14-nanometer |
0.05 |
0.0588 |
|
Samsung 14-nanometer |
0.064 |
0.080 |
Data sources: EETimes, ElectronIQ, Intel
Putting this into context, Intel's high density bitcell takes up roughly 78% of the area of Samsung's. Its low power one takes up 73.5% of the area that Samsung's does. As far as process densities go, at least if these SRAM bitcell sizes are representative, Intel's 14-nanometer process looks to be the clear winner.
Does this matter?
While the "battle of the processes" is certainly interesting and a hotly debated topic, it's important to keep in mind that manufacturing process is simply an enabler for good processor designs. There's no doubt that Intel's 14-nanometer process will be used to good effect in its PC and server offerings since Intel's design capabilities in those markets are second to none, but the open question has been, and continues to be, mobile.
According to roadmaps presented at Intel's 2014 investor meeting, Intel plans to roll out its first 14-nanometer tablet chip in 2015 and then a top-to-bottom family of 14-nanometer phone/tablet processors in 2016. If Intel can leverage this density edge across its products to offer more features/functionality for a lower cost than its competitors can, then this process lead could translate into a real advantage in mobile.
Whether Intel ultimately pulls that off, unfortunately, won't be known until 2016 rolls around.
