A while ago, Intel (NASDAQ:INTC) disclosed its low-power server processor road map. The company talked about three major products aimed at lower power servers built on its 14-nanometer technology. Perhaps the most interesting of the parts is a chip previously referred to as "Broadwell SoC" that Intel disclosed will be branded Xeon D.

Intel has offered system-on-chip products based on its lower power/performance Atom cores, but had not traditionally done so with its "big core" chips. With Xeon D, Intel was finally expected to remedy this. However, a careful examination of details provided by CPU World here shows Xeon D might not be a "true" system-on-chip.

Another one of these two-chip deals?
CPU World provided the following description of the Xeon D processor based on a block diagram seen by the site:

Broadwell-DE chips will have up to 8 CPU cores, an Integrated I/O block, a dual-channel memory controller, and PCH logic.


The I/O block will provide 24 lanes of PCI-e 3.0 interface, and 10Gb Ethernet interface. The PCH will have 6 SATA 3.0 ports, USB 3.0 and USB 2.0 ports, extra 1 GB Ethernet controller, and 8 lanes of PCI-e 2.0.

Notice that CPU World made sure to mention that the I/O block is "integrated" -- this seems to indicate the "PCH logic" is found on a separate chip. Intel does this with its Ultrabook-focused PC processors: integrates key performance-sensitive elements onto the main chip but then places less performance-sensitive parts on an auxiliary piece of silicon.

The efficiency impact
The widely noted problem with this approach is that Intel typically builds the auxiliary chip on older manufacturing technology. On the currently shipping Broadwell-U parts for Ultrabooks and the Core M aimed at thin PCs and two-in-ones, that PCH is built on Intel's relatively old 32-nanometer process.

I believe that given the relatively quick development time of the Xeon D processor (according to one Intel employee's LinkedIn profile, the company seemingly aimed to "tape-in" the product in just a year), the PCH chip that is likely on-package will also be a 32-nanometer design.

Since the heavy-duty parts of the chip will be built on Intel's latest 14-nanometer technology, having these relatively less power-hungry functions on 32-nanometer technology should not be a showstopper. I do, however, think Intel would be wise to offer single-chip solutions built on leading-edge technology as soon as feasible.

Why was this route taken?
The schedule on Broadwell-DE was apparently quite aggressive. This, I believe, is due to the fact that Intel takes the ARM (NASDAQ:ARMH) server threat seriously and wants to make sure it doesn't leave any proverbial stone unturned. Going with a separate, likely 32-nanometer, PCH was probably the right move from a time-to-market perspective.

However, I believe either Skylake-DE or Cannonlake-DE (assuming these projects are also in the works) will wind up with everything integrated into a single piece of silicon. This should lead to power efficiency improvements, though I am not quite sure about the impact on production costs. At any rate, the stakes are so high in this market that I doubt that the incremental production cost of integrating a PCH with the system-on-chip is something that Intel's product planners spend too much time worrying about.