A little while back, KGI Securities' Ming-Chi Kuo (via DIGITIMES) claimed that Apple's (AAPL -0.78%) next-generation tablet processor, which is likely to be dubbed the A10X or A10X Fusion, will be manufactured using Taiwan Semiconductor Manufacturing Company's (TSM 0.47%) 10-nanometer technology.
By contrast, the A10 Fusion chip inside of the recently announced iPhone 7 and iPhone 7 Plus, is manufactured using TSMC's more mature 16-nanometer manufacturing technology.
In this column, I'd like to offer up a potential explanation for why Apple may opt to adopt 10-nanometer for A10X.
A question of economics
According to Apple, the A10 Fusion chip is made up of 3.3 billion transistors. I estimate that on TSMC's 16-nanometer manufacturing technology, this chip will be quite large.
To estimate just how large the A10 Fusion is, note that the Apple A8 chip -- manufactured in TSMC's 20-nanometer technology -- packed more than 2 billion transistors (per Apple) into an area of 89 square millimeters (per Chipworks). Since TSMC's 16-nanometer technology didn't provide a meaningful area reduction over its 20-nanometer technology, a crude estimate of the A10 Fusion's die size based on the A8 would peg it at approximately 147 square millimeters.
That's gigantic for a smartphone chip. Heck, the majority of microprocessor giant Intel's (INTC 1.03%) laptop/desktop processors aren't even that big.
Given that the A10X is likely to cram in even more graphics cores and potentially other features over the A10, the chip would necessarily be well in excess of 150 square millimeters in TSMC's 16-nanometer technology.
This would be doable, but it could be quite expensive.
A move to 10-nanometer should help costs
The A10X chip implemented in TSMC's 10-nanometer technology would be significantly smaller than the same chip manufactured in TSMC's 16-nanometer technology. Assuming that the area reduction that 10-nanometer brings more than offsets the wafer cost increase associated with moving from 16-nanometer to 10-nanometers, the A10X should be cheaper to build on 10-nanometers.
Another factor that could further tilt costs in favor of the 10-nanometer node for the A10X would be yields. TSMC's 16-nanometer technology should be quite mature at this point, but it is well known that -- all else equal -- manufacturing yields of larger chips tend to be worse than those of smaller chips.
Assuming that TSMC's 10-nanometer technology is generally healthy when it comes time to ramp the A10X into production, yields on A10X on 10-nanometer may simply be better than yields of a hypothetical, equivalent A10X on TSMC's 16-nanometer technology.
There's a performance/power benefit, too
Although the main benefit in transitioning from 16-nanometer to 10-nanometer should be cost, TSMC does claim some performance/power benefits to its 10-nanometer technology relative to its 16-nanometer technology. The performance benefit should allow Apple to wring out a bit more performance than it otherwise would have been able to on the 16-nanometer technology.
Expect a performance monster with A10X
Apple's A10 Fusion is already a monster mobile chip, and I suspect that the iDevice maker has something very impressive cooking with its next-generation iPad chip. Apple's chip designs are generally impressive irrespective of the manufacturing technology used, but the transition to 10-nanometer should help with both cost and performance.