According to the technical program for the upcoming VLSI Symposium, Intel (INTC +6.32%) plans to detail its 14-nanometer system-on-chip manufacturing technology. This follows the company's initial 14-nanometer disclosures at the International Electron Devices Meeting in December 2014.
Although the full paper won't be published until June, when the conference is expected to take place, the company has provided key technical details in the summary provided in the aforementioned technical program.
Let's take a look at what Intel's got here.
Impressive density
Intel has talked a lot about the density of its 14-nanometer manufacturing technology relative to what its competitors in the semiconductor foundry landscape have been able to deliver with their respective 14/16-nanometer technologies. The company reports that it is delivering a high density SRAM cell -- a common structure -- in an area of just 0.0499 square micrometers.
Competitors TSMC (TSM 0.28%) and Samsung (NASDAQOTH: SSNLF) have reported that high density SRAM cells implemented in their respective 16-nanometer and 14-nanometer processes take areas of 0.070 square micrometers and 0.064 square micrometers.
The density that Intel has been able to achieve here is, in my view, quite competitive.
Good performance at low voltage
Intel says that at 100 nA/um leakage current, its high performance 14-nanometer transistors deliver NMOS/PMOS saturated drive currents of 1.3mA/um and 1.2mA/um, respectively (higher is better). These numbers, according to Intel, represent improvements of 37% and 50%, respectively, over what it achieved with its 22-nanometer technology.
Intel also discussed the drive currents of its ultra-low power NMOS/PMOS transistors at 15pA/um leakage, saying that it has achieved 0.50 mA/um and 0.32 mA/um, respectively.
Note that these numbers are all at 0.7 volts.
Samsung, sadly, hasn't published more details of its 14-nanometer technology, but TSMC did publish saturated drive currents of its 16-nanometer process at IEDM in late 2013. I can't get a good estimate of what drive currents TSMC is reporting at the 15pA/um leakage level from the plot found in the paper, but at the 100 nA/um level, TSMC reported NMOS/PMOS saturated drive currents below what Intel reported:
Source: TSMC paper with author annotation.
Also keep in mind that these transistors in TSMC's paper were operating at 0.75 volts -- 0.05 volts higher than what the Intel transistors required.
Can't forget analog
Intel says that its 14-nanometer system-on-chip manufacturing technology includes a "full suite of analog, mixed-signal, and RF features [which] are also supported." This should come in handy for the company's mobile ambitions, as the company has expressed a desire to move its entire wireless chip portfolio (which relies heavily on analog, mixed signal, and/or RF features) from being manufactured at third-party chip manufacturers.
What does this mean?
I believe that Intel has very impressive chip manufacturing technology that should be very well suited to building competitive system-on-chip products aimed at many different segments. In particular, though, Intel's 14-nanometer technology should give it a performance edge over mobile competitors building chips on competing 14/16-nanometer technologies.
What will be key for Intel now, though, is translating this best-in-class manufacturing technology into best-in-class mobile chip architectures that arrive at the marketplace in a timely fashion -- something that has proven difficult for the chip giant.
To illustrate this, Intel's Cherry Trail chip, built on the very 14-nanometer system-on-chip manufacturing technology discussed here, isn't competitive with chips such as the Apple (AAPL +1.84%) A8X (built on TSMC 20-nanometer technology) and the 14-nanometer Samsung Exynos 7420.
Intel's next mobile product built on this technology, codenamed Broxton, is scheduled to arrive in 2016. As an Intel bull, I'm hoping that the Broxton definition and implementation teams took full advantage of all that this 14-nanometer process has to offer.
