The TSMC-built Apple A9 in all of its glory. Image credit: Chipworks.
Generally speaking, in order to improve the performance of a system-on-chip and/or add new functionality, chip architects need to add additional transistors ("building blocks" of a chip) to the design.
One of the nice things about chip technology is that every few years or so, the companies that actually build chips roll out new manufacturing technologies that allow chip designers to pack more transistors into a given silicon footprint.
Ideally, the increased costs associated with making transistors smaller (which manifests itself as an increase in the cost per area of chip) is offset by the fact that far more transistors can fit into a given area.
When Apple (AAPL +0.04%), which designs its own processors for use in its iPhone/iPad products, moved from the A7 to the A8, it was able to take advantage of TSMC's (TSM +1.45%) new 20-nanometer manufacturing technology. This technology allowed Apple to more than double the number of transistors inside of the A8 relative to the A7 while also allowing the A8 to come in slightly smaller than the A7.
With the A9, however, Apple used new 14/16-nanometer technologies that delivered big improvements in transistor performance, but not much in the way of transistor area reduction. This meant the added functionality crammed into the A9 chip led to a larger chip than the A8.
For its upcoming A10 chip, Apple will once again be required to deliver a new, innovative chip without the aid of a transistor shrink as it will be built on TSMC's 16-nanometer process.
The question that I would like to explore here is, "How large will Apple make its A10 chip?"
Understanding the factors at play
Generally speaking, adding transistors to a design lowers the number of chips per wafer. Larger chips are often harder to yield than smaller chips, as the figure below illustrates:
Source: Integrated Circuit Engineering Corp.
In addition to the increased costs associated with adding more transistors/die area, a greater number of transistors can lead to higher power consumption.
That being said, even though the A10 is expected to be built on the same manufacturing technology as one variant of the prior generation A9 (the A9 is built by both TSMC and Samsung), TSMC has likely learned a lot from processing all of those A9/A9X wafers. This suggests that by the time the A10 goes into production (which shouldn't be long now), TSMC will have improved yields on its 16-nanometer process.
These improved yields should allow Apple to increase the die size of its A10 chip while at the same time keeping per-chip costs in check.
How big might Apple make the A10, then?
In going from the A8 to the A9, Apple grew chip size from 89 square millimeters on TSMC's 20-nanometer process to 104.5 square millimeters on TSMC's newer (and more complex) 16-nanometer process. That's a solid 17.4% increase in die size.
In light of this, I expect Apple gave its chip designers another 15-20% die area to use on the A10. If I'm right, teardowns should reveal a chip with a die size in the range of 120 to 125 square millimeters.
What might Apple do with that additional silicon real-estate?
A typical A-series chip features a lot of individual intellectual properties, including CPU cores, graphics cores, memory controller, image signal processor, sensor hub, and so on.
The big ticket intellectual properties that individually consume significant die area, though, are the graphics and CPU complexes.
According to AnandTech, the graphics block on the A8 measures in at 19.1 square millimeters. The two CPU cores take up 12.2 square millimeters. In an analysis of the A9 chip published in EETimes, the author estimates the graphics block takes up 27 square millimeters and the CPU cores take up approximately 13 square millimeters.
With the A10, I think we will see more of the same. The CPU cores will grow slightly (I don't think we will see the addition of a third CPU core) and the graphics processor will grow more significantly.
Indeed, I wouldn't be surprised to see Apple move from a six-cluster graphics processor in the A9 to an eight cluster graphics processor in the A10.
Apple will probably move to higher resolution displays with the iPhone 7 and 7 Plus (my guess is 1080p-class and 1440p-class displays, respectively). So, to make sure games and other 3D-graphics-intensive applications run well even at higher resolutions, additional graphical horsepower in the form of a larger graphics configuration should be a great way to spend those extra transistors.
