A modern processor, whether it powers a toaster or a supercomputer, is made up of building blocks known as transistors. Generally speaking, companies that develop transistors aim to do two things with each successive generation: make them smaller, and thus cheaper, and make them more power efficient.
Intel (INTC 2.20%) spent the last couple of years drilling into the minds of investors that it has a fundamental cost-per-transistor advantage over its manufacturing competitors, TSMC (TSM +0.40%) and Samsung (NASDAQOTH: SSNLF).
This advantage, per the company, stems from the fact that Intel's 14-nanometer process is "denser" than the 14/16-nanometer technologies fielded by its competition. After all, given a fixed wafer cost, the more transistors a company can pack into a given area, the cheaper each transistor is.
However, there is reason to doubt Intel's claims of cost-per-transistor superiority. Allow me to explain.
A9X versus Core m
According to Apple (AAPL 1.45%), the A8X chip that it debuted with the iPad Air 2 back in 2014 packed about 3 billion transistors in an area that was later discovered to be approximately 122 square millimeters. The follow-on A9X, built in a more advanced TSMC (TSM +0.40%) 16-nanometer process that didn't bring a material area shrink from the 20-nanometer process used to build the A8X, was quite a bit larger at 147 square millimeters.
I think it's safe to say that the A9X has even more than three billion transistors -- let's call it 3.6 billion (I'm assuming transistor count increase is proportional to die size increase).
In contrast, Intel's Broadwell Core m processor built on the company's 14-nanometer technology packs 1.3 billion transistors and occupies an area of 82 square millimeters.
Intel did not disclose the transistor counts of the latest Skylake-based Core m chip, but the die size is believed to be about 99 square millimeters. Intel also indicated at its most recent investor meeting that the Skylake Core m is a slightly denser than the Broadwell Core m processor. For the sake of this comparison, let's assume that the Skylake part packs around 1.56 billion transistors.
The cost per transistor clearly favors A9X
If we assume that TSMC's 16-nanometer wafer costs are equivalent to Intel's 14-nanometer wafer costs (this is actually not realistic; Intel's wafer costs are almost certainly a good degree higher), then the cost-per-transistor metric is clearly in favor of the 16-nanometer part. Indeed, Apple appears to have packed in more than twice as many transistors into the A9X as Intel did in the Skylake Core m, but the die size is only about 50% larger.
If we assume that Intel's wafer costs are even higher than TSMC's 16-nanometer wafer costs (a much more likely scenario), TSMC has an even larger advantage.
Intel's explanation
At Intel's 2015 investor meeting, the company's technology chief explained that once one normalizes the transistor areas for transistor composition (some transistor types take up much more area than others), Intel's 14-nanometer technology has a clear density/area lead over the competition.
The implication, of course, is that if two skilled chip teams implemented the same chip in the two different processes, Intel's chip would be smaller and ultimately more cost effective.
This explanation seems quite plausible. However, Daniel Nenni of SemiWiki brought up a point a while ago that it's difficult to dismiss: If transistor composition is critical to getting an accurate comparison of chip densities, then why not compare two parts with roughly the same power/performance targets?
In particular, the question that he asks is essentially: Why didn't Intel disclose both transistor count and die size for its low-power Cherryview (Atom) system-on-chip, which is aimed at just about the same power target as the Apple A9/A9X? The compositions in this case should be more comparable.
The fact that Intel hasn't disclosed transistor counts for either its 22-nanometer or 14-nanometer Atom processors certainly serves as a potential yellow flag with respect to Intel's claims of cost-per-transistor superiority.
