Image source: Intel.
For years now, Intel (INTC +4.89%) has been boasting that its current 14-nanometer and upcoming 10-nanometer chip manufacturing technologies can be used to create more densely packed chips than competing technologies from Taiwan Semiconductor Manufacturing Company (TSM 0.72%). Increased chip density, Intel claims, allows for a lower cost per transistor, ultimately meaning that a denser technology can enable a chip with more features than the same chip built on a less-dense technology for the same cost, or the same chip built more cheaply.
Indeed, Intel claimed at a presentation earlier this year that its 10-nanometer manufacturing technology offers "close to a full generation lead in logic density" compared to competing 10-nanometer technologies.
I don't disbelieve Intel's claims comparing its 10-nanometer technology to competing 10-nanometer technologies. It does appear that the company's 10-nanometer technology can deliver significantly smaller chip areas than competing 10-nanometer technologies. However, Intel has completely ignored, at least in its public messaging, the fact that its 10-nanometer technology will be going up against TSMC's 7-nanometer technology, not TSMC's 10-nanometer technology.
As luck would have it, TSMC recently disclosed a key piece of information about its 7-nanometer technology that essentially proves that Intel's lead in chip density is more or less a thing of the past.
TSMC's 7-nanometer SRAM cell
One helpful way to compare the relative densities of two processes is to build a similar structure -- often, a type of memory known as an SRAM. Intel disclosed a while back that a high-density SRAM cell in its 14-nanometer manufacturing technology measures in at 0.0499 square micrometers. This was significantly better than what TSMC was able to achieve with its 20-nanometer and 16-nanometer technologies.
Recently, however, TSMC disclosed that a high-density SRAM cell implemented in its 7-nanometer manufacturing technology measures in at just 0.027 square micrometers -- nearly half of the size of the comparable structure implemented in Intel's 14-nanometer technology. In order for Intel's 10-nanometer technology to simply achieve parity with what TSMC is delivering with its 7-nanometer technology, it will need to shrink its high-density SRAM cell by a factor of 0.541 times. Scaling beyond that should put it in the lead.
Intel's 10-nanometer should be roughly as dense as TSMC's 7-nanometer tech
If we look at the last couple of generations of high-density SRAM cell scaling between successive Intel processes, we see that a scaling factor of approximately 0.54 times is essentially the norm:
|
Intel Mfg. Tech |
High Density SRAM Cell Size (square micrometers) |
Scaling from previous |
|---|---|---|
|
45nm |
0.346 |
0.608x |
|
32nm |
0.171 |
.494x |
|
22nm |
0.092 |
0.538x |
|
14nm |
0.0499 |
0.541x |
Source: Intel.
At 45nm, Intel's SRAM cell scaling was quite poor, but at 32nm, it delivered a very good shrink. At the 22-nanometer and 14-nanometer generations, it delivered reasonable, but less than 0.5 times, shrinks. As long as Intel hits a similar shrink factor to what it achieved with its 22-nanometer and 14-nanometer processes, then its 10-nanometer technology should be competitive on SRAM cell size/gate density to TSMC's 7-nanometer technology.
What Intel won't be able to claim is a "full generation lead" over TSMC as it had previously been able to do
The new reality for Intel
As a result of the delays that the company saw with its 14-nanometer and subsequent 10-nanometer technologies, Intel has managed to take what was a roughly two-year leadership position in chip area and essentially fall to parity with TSMC. To make matters worse, there's no real way for Intel to regain a leadership position here, especially not on the path that the chipmaker is currently on.
TSMC is now, for all intents and purposes, "caught up" with Intel in terms of chip density. From its public statements, it plans to continue to scale down its chip area every two years.
Intel, on the other hand, says that it plans to use its 10-nanometer technology for three full generations -- though it will improve the transistor performance with each generation. This means that, at best, Intel is merely keeping pace with TSMC in terms of area scaling.
Business implications
From a business perspective, this lack of clear chip-area leadership will probably impact its contract chip manufacturing efforts the most. Intel says it's interested in targeting two key areas with said efforts -- mobile devices and networking infrastructure. Should Intel not manage to fumble its transistor performance lead as it did its chip area lead, then its technologies may still be attractive to customers willing to pay for additional performance in networking infrastructure.
However, given how valuable chip area/density is in the majority of mobile applications, particularly as they are so cost sensitive, a lack of leadership on this metric may make it unattractive for potential customers to leave a proven supplier (e.g. TSMC) for an unproven player like Intel.
